Voice Recognition Acquisition and Storage System using VHDL and the DE1-SoC FPGA

Arellanos E.; Remigio L.D.; Marquez J.L.O.; Nunez M. · Proceedings of the 2024 IEEE 31st International Conference on Electronics, Electrical Engineering and Computing, INTERCON 2024 (2024) · DOI: 10.1109/intercon63140.2024.10833462

Resumen

This paper presents the design of a voice acqui-sition and recognition system in VHDL, mainly optimized for FPGA DE1-SoC. The system implements advanced digital signal processing techniques combined with classification through the K-Nearest Neighbors (KNN) algorithm. The system operates at a 320 kHz sampling rate, with a latency of 10 ns and power consumption of 1.2 W. The design enhances precision and noise rejection through the use of Hamming windows and integer-based processing. Future improvements will focus on the implementation of neural networks to replace the KNN algorithm and further increase system accuracy.

Instituciones: Universidad Tecnológica del Perú; Universidad de Ingeniería y Tecnología