A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures

Marques C.M.; Brendler L.H.; Wrobel F.; Zimpeck A.L.; Bartra W.E.C.; Butzen P.F.; Meinhardt C. · Proceedings - 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2023 (2023) · DOI: 10.1109/sbcci60457.2023.10261665

Resumen

Building the devices on a Silicon on Insulator layer has proven to be one of the best manufacturing alternatives. However, radiation effects are still a challenge to nanometer technologies. This work evaluates three SRAM cells: 6T, 8T, and DICE considering a 28 nm FDSOI process. This work simulates a structure of 256 bit-cells, including the auxiliary circuits, to evaluate the SRAM architecture. The topologies were evaluated for robustness to Single Event Upsets (SEU), considering internal faults in the cell, and to Single Event Transient (SET) faults derivate from the propagation of a fault that occurs in the auxiliary circuits. We are considering the fault effects during four operations: Hold, Read, Write, and Open-Access Mode (OAM). For the 6T and DICE, the cells that remain in OAM during the execution of a Read or Write operation are over 5x more sensitive than Hold. The 8T cell presents a 6% lower robustness for SEU than the 6T. However, the 8T cell shows the best result during read and OAM, being 40% more robust than the DICE cell.

Instituciones: Pontificia Universidad Católica del Perú